1. Field of the Invention
The present invention relates to a semiconductor integrated circuit which comprises a storage circuit including a storage section on a semiconductor substrate. The present invention relates particularly to a semiconductor integrated circuit which comprises a storage circuit, such as a register file and an SRAM (Static Random Access Memory), and uses a substrate potential effect.
2. Description of the Related Art
In terms of a semiconductor integrated circuit which comprises a storage circuit, there exists a semiconductor integrated circuit which is configured as shown in FIG. 21 (for example, refer to Japanese Patent Application Laid-Open (JP-A) No. 11-39879 (paragraph 0018, FIG. 3)). The storage section comprises two inverters 210 and 220 in this semiconductor integrated circuit. One inverter 210 is comprised of a P-channel MOS FET 211 and an N-channel MOS FET 212. The other inverter 220 is comprised of a P-channel MOS FET 221 and an N-channel MOS FET 222.
In addition, there is provided a circuit which selectively changes a substrate potential applied to a semiconductor substrate in which the P-channel MOS FETs 211 and 221, and the N-channel MOS FETs 212 and 222 are formed. This circuit is comprised of a switch consisting of P-channel MOS FETs 231 and 232, N-channel MOS FETs 241 and 242, and switches the substrate potential applied to the substrate with switching control signals 251 and 252.
Thus, the circuit changes a threshold voltage of each of MOS FETs 211, 212, 221, and 222 depending upon the storage section being in an active mode or a sleep mode, so that power consumption is suppressed with maintaining high-speed operation at a required time.
When selectively changing the substrate potential of the storage section, a forward bias is applied during staying in an active mode, and a back bias is applied during staying in a sleep mode as shown in FIG. 21. It is therefore possible to achieve an improvement in speed of circuit operation and a reduction in leakage current, respectively, as compared with a case where the substrate potential of the storage section is not changed.
However, the storage circuit such as SRAMs or the like includes a writing section and a reading section for writing/reading data in/from the storage section other than the storage section, and includes many writing sections and reading sections particularly in a multi-port memory. In this case, circuit operation mainly depends on the P-channel MOS FET and the N-channel MOS FET in the writing section and the reading section rather than the storage section. Therefore, in order to achieve an improvement in speed of circuit operation and a reduction in leakage current, it is insufficient just to control the substrate potential only for the P-channel MOS FET and the N-channel MOS FET in the storage section like a prior art.
In addition, there exist operations in connection with the writing section and the reading section other than an active mode and a sleep mode of the storage section as a circuit operation in the semiconductor integrated circuit including the storage circuit, but a method of the prior art can not set how to apply the substrate potential suitable for these operations.
Moreover, an isolation region is required in order to isolate the substrate, but reference is not made about an increase in layout circuit area because of this isolation region in the prior art.